Extended message signaled interrupts (msi) message data

ABSTRACT

Extended message signaled interrupts (MSI) data are disclosed. In one aspect, MSI bits are modified to include a system level identifier. In an exemplary aspect, an upper sixteen bits of the MSI message data are modified to be the system level identifier. By providing the system level identifier within the MSI message data, an interrupt controller can verify the interrupt source.

PRIORITY APPLICATIONS

The present application is a continuation of and claims priority to U.S.patent application Ser. No. 15/184,124, filed on Jun. 16, 2016, andentitled “EXTENDED MESSAGE SIGNALED INTERRUPTS (MSI) MESSAGE DATA,”which is incorporated herein by reference in its entirety.

The '124 application claims priority to and the benefit of U.S.Provisional Patent Application Ser. No. 62/182,800, filed on Jun. 22,2015, and entitled “ENHANCED MESSAGE SIGNALED INTERRUPTS FOR SYSTEMIDENTIFICATION,” which is incorporated herein by reference in itsentirety.

The '124 application also claims priority to and the benefit of U.S.Provisional Patent Application Ser. No. 62/243,850, filed on Oct. 20,2015, and entitled “EXTENDED MESSAGE SIGNALED INTERRUPTS (MSI) MESSAGEDATA,” which is incorporated herein by reference in its entirety.

BACKGROUND I. Field of the Disclosure

The technology of the disclosure relates generally to a PeripheralComponent Interconnect (PCI) communication bus.

II. Background

Mobile communication devices have become increasingly common in modernsociety. The increasing popularity of such mobile communication devicesis driven, in part, by the increased functionality available on thesedevices. Such increased functionality is enabled by the inclusion ofever more complex integrated circuits (ICs) within the mobilecommunication devices. As the number and complexity of the ICs withinthe mobile communication devices has increased, so has the need for thevarious ICs to communicate with one another.

Several standards have been published outlining various protocols thatallow ICs to communicate with one another. A popular protocol is thePeripheral Component Interconnect (PCI) protocol, which comes in variousflavors, including the PCI express (PCIe) protocol. While useful as ICto IC communication protocols, the PCI and PCIe protocols may also beused to couple a mobile terminal to a remote device through a cable orother connector.

The PCIe protocol defines various message types that may be sent andreceived across a PCIe-compliant bus. One such message type is aninterrupt. An interrupt signal is provided to a host, and the host mustascertain if a source of the interrupt signal is authorized to requestthe interrupt. Currently, a root complex in the host strips anidentifier from a header of the interrupt signal and provides theidentifier to a memory management unit using a separate signal in a sidechannel. The identifier is also routed in the system to an interruptcontroller in the side channel. Use of such side channels may increasepower consumption as well as require additional conductive elements.Accordingly, there is a need to reduce reliance on the side channel toprovide such source identifiers. In addition to the identifier, othermessages containing different information may be sent on side channelsand the need to reduce reliance on such side channels is applicable tothese other messages as well.

SUMMARY OF THE DISCLOSURE

Aspects disclosed in the detailed description include extended messagesignaled interrupts (MSI) message data. Exemplary aspects of the presentdisclosure contemplate using the extended MSI message data foradditional information that assists in processing interrupts byreplacing unused bits in the extended MSI message data with meaningfuldata. In one exemplary aspect, MSI bits are modified to include theadditional information, which may be a system level identifier (whichmay be referred to sometimes as a source identifier). In an exemplaryaspect, an upper sixteen bits of the extended MSI message data aremodified to contain the additional information, which may include thesystem level identifier, whose size may be less than the full sixteenbits, but may be up to the full sixteen bits. By providing the systemlevel identifier within the extended MSI message data, an interruptcontroller can verify an interrupt source. Other exemplary aspects mayprovide interrupt priority information or interrupt moderationinformation in the extended MSI message data. By providing theadditional extended MSI message data in a body of historically unusedMSI bits, the need for side channels may be reduced, which simplifieswiring and reduces power consumption.

In this regard, in one aspect, a method of passing information in aPeripheral Component Interconnect (PCI) express (PCIe) system isdisclosed. The method includes receiving at a host a signal. The signalincludes a header. The signal also includes a body. The body includesextended MSI message data in at least one of a first sixteen bits from aPCIe endpoint. The method also includes extracting, at a root complex ofthe host, the body from the signal to form an MSI vector with theextended MSI message data still in the body of the MSI vector. Themethod also includes passing over a System Network on a Chip (SNoC) theMSI vector to an interrupt controller in the host with the extended MSImessage data still in the body of the MSI vector.

In another aspect, a method of passing information in PCIe system isdisclosed. The method includes generating at a slave in a PCIe system, asignal. The signal includes a header. The signal also includes a body.The body includes extended MSI message data in at least one of a firstsixteen bits. The method also includes sending the signal to a host ofthe PCIe system.

In another aspect, a host in a PCIe system is disclosed. The hostincludes a SNoC bus. The host also includes a PCIe bus interface. ThePCIe bus interface is configured to be coupled to a PCIe bus. The PCIebus interface is further configured to receive a signal having extendedMSI message data from the PCIe bus. The host also includes an interruptcontroller coupled to the SNoC bus. The host also includes a memorymanagement unit coupled to the SNoC bus. The host also includes a rootcomplex coupled to the PCIe bus interface and the memory managementunit. The root complex is configured to extract a body from the signalto form an MSI vector with the extended MSI message data still in thebody of the MSI vector and pass the MSI vector to the interruptcontroller with the extended MSI message data still in the body of theMSI vector through the memory management unit and the SNoC bus.

In another aspect, a slave in a PCIe system is disclosed. The slaveincludes a PCIe bus interface configured to be coupled to a PCIe bus.The slave also includes a capability register. The capability registerincludes information indicating that a slave can use extended MSImessage data. The slave also includes a control system. The controlsystem is configured to detect an interrupt need condition. The controlsystem is also configured to assemble a signal including a header and abody including the extended MSI message data. The control system is alsoconfigured to send the signal to a host over the PCIe bus.

In another aspect, a PCIe system is disclosed. The PCIe system includesa PCIe bus. The PCIe system also includes a PCIe slave. The PCIe slaveincludes a slave PCIe bus interface coupled to the PCIe bus. The PCIeslave also includes a slave control system. The slave control system isconfigured to detect an interrupt need condition. The slave controlsystem is also configured to assemble a signal including a header andbody including extended MSI message data. The slave control system isalso configured to send the signal to a host over the PCIe bus. The PCIesystem also includes the host. The host includes a SNoC bus. The hostalso includes a host PCIe bus interface coupled to the PCIe bus. Thehost PCIe bus interface is further configured to receive the signal. Thehost also includes an interrupt controller coupled to the SNoC bus. Thehost also includes a root complex coupled to the host PCIe businterface. The root complex is configured to extract the body from thesignal to form an MSI vector with the extended MSI message data still inthe body of the MSI vector and pass the MSI vector to the interruptcontroller with the extended MSI message data still in the body of theMSI vector through the SNoC bus.

In another aspect, a method of identifying a signal source in a PCIesystem is disclosed. The method includes receiving at a host a signalhaving a requester identifier in a header and a source identifier in abody from a PCIe endpoint. The method also includes at a root complex ofthe host, removing the requester identifier. The method also includesextracting the body to form an MSI vector with the source identifierstill in the body of the MSI vector. The method also includes passingover a SNoC the MSI vector to an interrupt controller in the host withthe source identifier still in the body of the MSI vector.

In another aspect, a method of identifying a signal source in a PCIesystem is disclosed. The method includes generating at a slave in a PCIesystem, a signal. The signal includes a header including a requesteridentifier. The signal also includes a body including a sourceidentifier. The method also includes sending the signal to a host of thePCIe system.

In another aspect, a host is disclosed. The host includes a businterface configured to be coupled to a PCIe bus. The host also includesa root complex coupled to the bus interface. The root complex isconfigured to receive a signal containing a requester identifier in aheader of the signal and a source identifier from the bus interface. Theroot complex is also configured to remove the header from the signal.The root complex is also configured to send an MSI vector to aninterrupt controller containing a body of the signal including thesource identifier in a body of the MSI vector. The interrupt controlleris configured to receive the MSI vector containing the source identifierin the body of the MSI vector.

In another aspect, a slave in a PCIe system is disclosed. The slaveincludes a PCIe bus interface configured to be coupled to a PCIe bus.The slave also includes a capability register including informationindicating that a slave can use a source identifier in a body of aninterrupt signal. The slave also includes a control system. The controlsystem is configured to detect an interrupt need condition. The controlsystem is also configured to assemble a signal including a headerincluding a requester identifier and a body including the sourceidentifier. The control system is also configured to send the signal toa host over the PCIe bus.

In another aspect, a method of identifying a signal source is disclosed.The method includes receiving at a host a signal having a requesteridentifier in a header and a system level identifier in a body from aPCIe endpoint. The method also includes, at a root complex of the host,removing the requester identifier. The method also includes extracting abody to form an MSI vector with the system level identifier still in thebody of the MSI vector. The method also includes passing over a SNoC theMSI vector to an interrupt controller in the host with the system levelidentifier still in the body of the MSI vector.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram of an exemplary Peripheral ComponentInterconnect (PCI) express (PCIe) system with aspects of a centralprocessing unit (CPU) further illustrated;

FIG. 2 illustrates a conventional message signaled interrupt (MSI)signal or packet that is sent from a PCIe endpoint to a PCIe host;

FIG. 3 illustrates an MSI signal or packet according to an exemplaryaspect of the present disclosure with extended MSI message data in abody of the MSI signal;

FIG. 4 illustrates an exemplary signal message flow diagram between theelements of FIG. 1;

FIG. 5 illustrates an exemplary System Network on Chip (SNoC) packet orMSI vector that may be sent from a root complex in a host to aninterrupt controller in the host with extended MSI message data thereinaccording to exemplary aspects of the present disclosure;

FIG. 6 is a flowchart illustrating an exemplary method associated withthe PCIe system of FIG. 1;

FIG. 7 is a flowchart illustrating a process of exchanging extended MSImessage data according to an exemplary aspect from a host sideperspective;

FIG. 8 is a flowchart illustrating a process of exchanging message dataaccording to an exemplary aspect from a slave side perspective:

FIG. 9 illustrates a simplified block diagram of a system where multipleendpoints share a single system level identifier; and

FIG. 10 is a block diagram of an exemplary processor-based system thatcan include the PCIe system of FIG. 1.

DETAILED DESCRIPTION

With reference now to the drawing figures, several exemplary aspects ofthe present disclosure are described. The word “exemplary” is usedherein to mean “serving as an example, instance, or illustration.” Anyaspect described herein as “exemplary” is not necessarily to beconstrued as preferred or advantageous over other aspects.

Aspects disclosed in the detailed description include extended messagesignaled interrupts (MSI) message data. Exemplary aspects of the presentdisclosure contemplate using the extended MSI message data foradditional information that assists in processing interrupts byreplacing unused bits in the extended MSI message data with meaningfuldata. In one exemplary aspect, MSI bits are modified to include theadditional information, which may be a system level identifier (whichmay be referred to sometimes as a source identifier). In an exemplaryaspect, an upper sixteen bits of the extended MSI message data aremodified to contain the additional information, which may include thesystem level identifier, whose size may be less than the full sixteenbits, but may be up to the full sixteen bits. By providing the systemlevel identifier within the extended MSI message data, an interruptcontroller can verify an interrupt source. Other exemplary aspects mayprovide interrupt priority information or interrupt moderationinformation in the extended MSI message data. By providing theadditional extended MSI message data in a body of historically unusedMSI bits, the need for side channels may be reduced, which simplifieswiring and reduces power consumption.

In this regard, FIG. 1 is a block diagram of an exemplary PeripheralComponent Interconnect (PCI) express (PCIe) system 100 configured tosupport exchange of extended MSI message data within a body of a signalfor extraction and use in an MSI vector. In particular, FIG. 1illustrates the PCIe system 100, which includes a host 102, which may bea central processing unit (CPU), a system on a chip (SoC), or the like.The host 102 is coupled to PCIe endpoints 104(1)-104(M) through a PCIebus 106. It should be appreciated that the PCIe protocol calls for apoint to point connection between host and endpoints, and thus, eachconnection may be considered its own bus. However, for the sake ofconvenience, the plurality of connections is termed the PCIe bus 106herein. Further, point to multi-point capability may be achieved throughuse of a hub or switch 108. As illustrated, PCIe endpoints 104(1)-104(N)are connected by point to point connections within the PCIe bus 106, andPCIe endpoints 104(N+1)-104(M) are coupled to the switch 108. It shouldbe appreciated that the PCIe system 100 may include multiple switches(not illustrated) or no switches (also not illustrated) withoutdeparting from the scope of the present disclosure. Likewise, the numberof endpoints coupled to any switch may vary without departing from thescope of the present disclosure. Each of the PCIe endpoints104(1)-104(M) may also be considered a slave relative to the host 102.

With continued reference to FIG. 1, each PCIe endpoint 104(1)-104(M)includes a respective slave PCIe bus interface 110(1)-110(M) that isconfigured to couple to the PCIe bus 106. Further, each PCIe endpoint104(1)-104(M) may include a control system 112(1)-112(M). The controlsystem 112(1)-112(M) may interoperate with a corresponding capabilityregister 116(1)-116(M). Capability identifiers may be stored therein,each capability having a unique capability identifier, which may be readby the host 12. While described as unitary capability registers, itshould be appreciated that the present disclosure also contemplatesbanks of capability registers, each register representing a differentcapability or subsets of a total number of capabilities withoutdeparting from the scope of the present disclosure. The general conceptof capability registers is well documented in the PCIe standard.Exemplary aspects of the present disclosure add a new capabilityregister as outlined below. Additionally, each PCIe endpoint104(1)-104(M) may have a corresponding configuration register118(1)-118(M).

With continued reference to FIG. 1, the host 102 may include a businterface 120, which allows signals to be transmitted onto or receivedfrom the PCIe bus 106. Note that given the point to point nature of thePCIe protocol, the bus interface 120 may include a plurality of point topoint interfaces. However, such individual interfaces are not shown forsimplicity. The host 102 further includes a PCIe root complex 122 thatcommunicates with a memory management unit 124. The memory managementunit 124 is coupled to a System Network on a Chip (SNoC) 126, which actsas an internal bus for the host 102. In particular, the memorymanagement unit 124 may communicate with an interrupt controller 128through the SNoC 126.

In conventional systems, if a PCIe endpoint generates an interrupt, thePCIe endpoint generates an MSI packet or signal 200 as illustrated inFIG. 2 and sends the MSI signal 200 to the PCIe root complex over thePCIe bus. The MSI signal 200 has a header 202 with a requesteridentifier 204 (referenced in drawings as requester ID) in a messagecontrol field 206 in the header 202. The MSI signal 200 further has adestination address 208 in the header 202 and a body 210. MSI messagedata 212 is contained in a final sixteen bits of the body 210. Forconventional systems, a first sixteen bits 214 of the body 210 arereserved and not used. With continued reference to a conventionalsystem, the PCIe root complex removes the header 202 from the MSI signal200 and passes the interrupt to the memory management unit with therequester identifier 204 being provided through a separate signal in aside channel. The memory management unit in turn passes the interrupt tothe interrupt controller over the SNoC maintaining the requesteridentification on a side channel. Additional information, such asinterrupt priorities and interrupt moderation, may likewise be includedin the header 202, but also may be stripped out by the PCIe root complexand sent to the interrupt controller through a side band. The use ofsuch side channels may require extra wiring, increase power consumptionas an additional channel must be driven, and otherwise be undesirable.

Exemplary aspects of the present disclosure eliminate the need for theside channel by including extended MSI message data in the body of theMSI signal. An exemplary MSI packet or signal 300 according to anexemplary aspect of the present disclosure is provided with reference toFIG. 3. As with the MSI signal 200 of FIG. 2, the MSI signal 300includes a header 302 with a requester identifier 304 (referenced indrawings as requester ID) in a message control field 306 in the header302. The MSI signal 300 further has a destination address 308 in theheader 302 and a body 310. MSI message data 312 is contained in a finalsixteen bits of the body 310. A first sixteen bits 314 of the body 310are used to hold extended MSI message data 316. In an exemplary aspect,the extended MSI message data 316 may be a source identifier or a systemlevel identifier. Note that the system level identifier does not have tobe the same as a device identifier, and in exemplary aspects, multipledevices may have the same system level identifier. In an exemplaryaspect, the system level identifier may be created by one of the PCIeendpoints 104(1)-104(M) of FIG. 1 by using its correspondingconfiguration register 118(1)-118(M). The content of this configurationregister 118(1)-118(M) may be set by software running on the host 102.Alternatively, the system level identifier may be the same as therequester identifier 304 provided by a PCIe enumeration process. Inother exemplary aspects, the extended MSI message data may be interruptpriority information or interrupt moderation information. In stillanother exemplary aspect, the extended MSI message data may beadditional data that would otherwise be put in the MSI message data 312.The extended MSI message data may then be preserved in the body of anMSI vector passed to the interrupt controller 128 without the need forthe side channels.

While it is particularly contemplated that the first sixteen bits 314 ofthe body 310 may be used to provide the system level identifier, thepresent disclosure is not so limited. In this regard, as alluded toabove, the body 310 may carry extended message data such as theinterrupt priority information, the interrupt moderation information(which may be used to aggregate a predetermined number of interruptsbefore executing an interrupt), or the like. Further, while it iscontemplated that the system level identifier may use all sixteen bitsof the first sixteen bits 314, the present disclosure is not so limited.That is, fewer than sixteen bits may be used for the system levelidentifier, and any remaining bits may be used to carry otherinformation such as the interrupt priority information, the interruptmoderation information, or the like. In still another aspect, the MSImessage data 312, which is normally only sixteen bits, may be expandedto use the full thirty-two bits of the body 310.

FIG. 4 illustrates a signal message flow diagram 400 between theelements of FIG. 1. For the sake of example, PCIe endpoint 104(1) isused, although it should be appreciated that any of the other PCIeendpoints 104(2)-104(M) could also operate in similar fashion. The host102 may have a PCIe driver 402 in the form of software running on aprocessor that initiates certain operations of the process associatedwith the signal message flow diagram 400. In this regard, afterenumeration (not illustrated), the PCIe driver 402 may cause the PCIeroot complex 122 to initiate a capability inquiry by sending endpoint(EP) ability capable signal 404. Then, the PCIe root complex 122 maysend an EP inquiry capable message 406 to the PCIe endpoint 104(1). ThisEP inquiry capable message 406 may cause capability register 116(1) tobe read. The PCIe endpoint 104(1) sends back an affirmative signal 408indicating that the PCIe endpoint 104(1) is capable of using extendedMSI message data. Based on the affirmative signal 408, the PCIe rootcomplex 122 may pass a continued affirmative signal 410 to the PCIedriver 402. The PCIe driver 402 may then generate an enable abilitysignal 412 that is sent to the PCIe root complex 122. The PCIe rootcomplex 122 then sends an enable ability command 414 to the PCIeendpoint 104(1) that instructs the PCIe endpoint 104(1) to use theextended MSI message data in the body 310 of the MSI signal 300. ThePCIe root complex 122 also sends a command 416 to the interruptcontroller 128 to configure the interrupt controller 128 to look for theextended MSI message data in the body of any MSI vector that theinterrupt controller 128 receives. Where the extended MSI message datais a system level identifier, software, such as access controlconfiguration software 418 resident in the memory management unit 124,may command that a write command be sent to the appropriateconfiguration registers 118(1)-118(M) to set the system level identifierthrough signal 420. While exemplary non-limiting aspects of the presentdisclosure provide the access control configuration software 418 in thememory management unit 124, the access control configuration software418 may likewise be present in a processor or controller in the host102. However, the present disclosure is not so limited, and thisfunction may be implemented in firmware in the host 102. Further, whilea processor or controller within the host 102 is one location for theaccess control configuration software 418, it should be appreciated thatthe functions of the access control configuration software 418 may beperformed outside the host 102.

With continued reference to FIG. 4, the signal 420 causes the PCIe rootcomplex 122 to send a set system level identifier signal 422 to the PCIeendpoint 104(1), which sets the system level identifier in theconfiguration register 118(1). A client driver 424, which may be a PCIedriver within the host 102, sets the message data into the appropriateregister in the PCIe endpoint 104(1) through signal 426. In an exemplarynon-limiting aspect, the client driver 424 may run on any processor orcontroller in the host 102 or may be positioned outside the host 102 asneeded or desired.

With continued reference to FIG. 4, the PCIe endpoint 104(1) generatesan interrupt signal 428 and sends the interrupt signal 428 to the PCIeroot complex 122 over the PCIe bus 106. The PCIe root complex 122 thenpasses a message payload with an MSI vector 430 to the memory managementunit 124. The memory management unit 124 then uses the SNoC 126 to passan MSI vector 432 with the extended MSI message data in the body of theMSI vector 432 to the interrupt controller 128. The interrupt controller128 then parses the MSI vector 432 and extracts the extended MSI messagedata, which may, for example, be the system level identifier. In theevent that the extended MSI message data is the system level identifier,the extracted system level identifier is compared to entities authorizedto request interrupts (for example, with a look-up table (notillustrated) or the like), and, if the system level identifier isauthorized, the interrupt controller 128 sends an interrupt authorizedsignal 434 to the memory management unit 124 for interrupt execution. Ifthe extended MSI message data includes data other than the system levelidentifier, the additional data is likewise within the body of the MSIvector 432 and used appropriately after extraction from the MSI vector432.

The MSI vector 432 contains MSI message data 500 and extended MSImessage data 502 as illustrated in FIG. 5. In an exemplary aspect, theMSI message data 500 is in the final sixteen bits of the MSI vector 432and the extended MSI message data 502 is in the first sixteen bits. Asnoted above, the extended MSI message data 502 may be the system levelidentifier, the interrupt priority information, the interrupt moderationinformation, additional MSI data, or the like. Further, while sixteenbits are available for the extended MSI message data 502, use of lessthan all sixteen bits is still within the scope of the presentdisclosure.

A flowchart of an exemplary process substantially similar to the signalmessage flow diagram 400 of FIG. 4 is provided in FIG. 6. In thisregard, process 600 presents a system level flowchart. The process 600begins with the PCIe root complex 122 sending a capability query to thePCIe endpoint 104(1) (block 602) (e.g., the EP inquiry capable message406). The PCIe root complex 122 receives a capability response (e.g.,the affirmative signal 408) from the PCIe endpoint 104(1) indicatingthat the PCIe endpoint 104(1) is capable of using the extended MSImessage data (e.g., the system level identifier) in the body 310 of theMSI signal 300 (block 604). The PCIe root complex 122 instructs the PCIeendpoint 104(1) to enable use of the extended MSI message data (block606) (e.g., the enable ability command 414). The PCIe root complex 122further configures the interrupt controller 128 to look for the extendedMSI message data 502 in the body of the MSI vector (block 608) (e.g.,the command 416).

With continued reference to FIG. 6, the PCIe endpoint 104(1) generatesthe interrupt signal 428 with the requester identifier 304 in the header302 and the extended MSI message data 316 in the body 310 of the MSIsignal, which is received at the PCIe root complex 122 (block 610). Atthe PCIe root complex 122, the PCIe root complex 122 removes the header302 and passes the interrupt to the memory management unit 124 (block612) (e.g., the MSI vector 432). The memory management unit 124 passesthe MSI vector 432 to the interrupt controller 128 over the SNoC 126(block 614). The interrupt controller 128 uses the extended MSI messagedata as indicated, which, if the extended MSI message data is a systemlevel identifier, the interrupt controller 128 verifies the interruptbased on the system level identifier (block 616). Once the interruptcontroller 128 verifies that the requesting entity is allowed tointerrupt the host, the interrupt controller 128 takes the appropriateinterrupt action(s).

While the process 600 of FIG. 6 illustrates an exemplary process of thepresent disclosure, FIGS. 7 and 8 provide host and slave point of viewflowcharts respectively. In this regard, FIG. 7 illustrates process 700.The process 700 begins when the PCIe system 100 of FIG. 1 starts andenumerates elements within the PCIe system 100 (block 702). Theenumeration process is well documented in the PCIe protocol and is notfurther discussed. The host 102 sends a capability inquiry to each ofthe PCIe endpoints 104(1)-104(M) (block 704). The host 102 receivescapability responses from the PCIe endpoints 104(1)-104(M) (block 706).Based on the capability responses received, the host 102 instructscapable endpoints of the PCIe endpoints 104(1)-104(M) to use extendedMSI message data (block 708). Note that at this point, the PCIe driver402 and the client driver 424 may populate extended message dataregisters and message data registers (note that these may be within theconfiguration registers 118(1)-118(M)) within the PCIe endpoints104(1)-104(M). In an exemplary aspect, the extended message dataregister is populated with a system level identifier or a sourceidentifier. As discussed above, this may be the same as or differentthan the identifier created during enumeration.

With continued reference to FIG. 7, the host 102 also configures theinterrupt controller 128 to use the extended MSI data in the body of theMSI vector (block 710). At some subsequent time, the host 102 willreceive the MSI signal 300 with the header 302 having the requesteridentifier 304 and the body 310 having the extended MSI message datatherein (block 712) over the PCIe bus 106. The PCIe root complex 122extracts the body 310 from the MSI signal 300 to form an MSI vector withthe extended MSI message data still in the body of the MSI vector (block714). The MSI vector is then passed over the SNoC 126 to the interruptcontroller 128 (block 716).

Similarly, FIG. 8 illustrates a process 800 from the slave point ofview. The process 800 begins with enumeration at the startup of the PCIesystem 100 (block 802). After enumeration, the slave receives acapability inquiry from the host 102 (block 804). The slave reads theappropriate capability register 116(1)-116(M) (block 806) and respondsto the capability inquiry with information indicating the slave iscapable of using the extended MSI message data (block 808). The slavereceives instructions to enable the use of extended MSI message data(block 810) (e.g., signal 414).

With continued reference to FIG. 8, at some subsequent time, the slavedetects an interrupt condition (block 812) and generates an interruptsignal with a header having a requester identifier and a body having theextended MSI message data in the first sixteen bits of the body (block814). The slave then sends the interrupt signal to the host 102 over thePCIe bus 106 (block 816).

By using the capability inquiry in the various processes 600, 700, and800, backwards compatibility may be maintained in that absent anaffirmative response (such as occurs when a legacy component isqueried), the ability is not enabled, and the extended MSI message datais not placed in the first sixteen bits of the MSI vector.

As alluded to above, multiple endpoints may have the same system levelidentifier. In this regard, FIG. 9 illustrates a block diagram of anexemplary PCIe system 900. The PCIe system 900 includes a host 902,which may be a CPU or other SoC. The PCIe system 900 further includesPCIe endpoints 904(1)-904(4). The host 902 is coupled to a switch 906through a PCIe bus 908. Note that the PCIe endpoints 904(1)-904(4) arecoupled to the PCIe bus 908 through the switch 906.

With continued reference to FIG. 9, the host 902 may include a businterface 910, which allows signals to be transmitted onto or receivedfrom the PCIe bus 908. The host 902 further includes a PCIe root complex912 that communicates with a memory management unit (referenced indrawings as MMU) 914. The memory management unit 914 is coupled to aSNoC 916, which acts as an internal bus for the host 902. In particular,the memory management unit 914 may communicate with an interruptcontroller 918 through the SNoC 916.

With continued reference to FIG. 9, PCIe endpoints 904(1) and 904(2)have the same system level identifier (SLI1) associated therewith. Thatis, the access control configuration software 418 has programedrespective configuration registers 920(1) and 920(2) with the samesystem level identifier. PCIe endpoint 904(3) has a second system levelidentifier (SLI2) in its configuration register 920(3), and PCIeendpoint 904(4) has a third system level identifier (SLI3) in itsrespective configuration register 920(4).

With continued reference to FIG. 9, the interrupt controller 918 has anMSI entries list 922 which may be programmed with which system levelidentifiers are allowed to perform which interrupts. Thus, extending onthe concept introduced in block 616 of FIG. 6, the interrupt controller918 receives the MSI vector address and extracts the system levelidentifier from the extended MSI message data. Using the MSI vectoraddress, the interrupt controller 918 compares the extracted systemlevel identifier to allowed system level identifiers in the MSI entrieslist 922, and, if there is a match, then the interrupt controller 918acts on the regular MSI data within the interrupt request.

The extended MSI message data according to aspects disclosed herein maybe provided in or integrated into any processor-based device. Examples,without limitation, include a set top box, an entertainment unit, anavigation device, a communications device, a fixed location data unit,a mobile location data unit, a mobile phone, a cellular phone, a smartphone, a tablet, a computer, a portable computer, a desktop computer, apersonal digital assistant (PDA), a monitor, a computer monitor, atelevision, a tuner, a radio, a satellite radio, a music player, adigital music player, a portable music player, a digital video player, avideo player, a digital video disc (DVD) player, an automobile, and aportable digital video player.

In this regard, FIG. 10 illustrates an example of a processor-basedsystem 1000 that can employ the PCIe system 100 illustrated in FIG. 1.In this example, the processor-based system 1000 includes one or morecentral processing units (CPUs) 1002, each including one or moreprocessors (not illustrated). The CPU(s) 1002 may have cache memory (notillustrated) coupled to the processor(s) (not illustrated) for rapidaccess to temporarily stored data. The CPU(s) 1002 is coupled to asystem bus 1004. As is well known, the CPU(s) 1002 communicates withother devices by exchanging address, control, and data information overthe system bus 1004. For example, the CPU(s) 1002 can communicate bustransaction requests to one or more memory controllers 1006.

Other devices can be connected to the system bus 1004. As illustrated inFIG. 10, these devices can include one or more display controllers 1008and one or more PCIe controllers 1010, as examples. The memorycontroller(s) 1006 may interoperate with memory units 1012 through oneor more memory interfaces 1014. Note that in an exemplary aspect, thememory interface(s) 1014 may be a PCIe bus, like the PCIe bus 106 ofFIG. 1. The display controller(s) 1008 may communicate with a display1016 through a display interface 1018. The display 1016 can include anytype of display, including, but not limited to, a cathode ray tube(CRT), a liquid crystal display (LCD), a plasma display, a lightemitting diode (LED) display, etc.

While not illustrated in FIG. 10, the processor-based system 1000 mayalso include a network interface device, which can be any deviceconfigured to allow exchange of data to and from a network (notillustrated). The network can be any type of network, including, but notlimited to, a wired or wireless network, a private or public network, alocal area network (LAN), a wireless local area network (WLAN), a widearea network (WAN), a BLUETOOTH™ network, and the Internet. The networkinterface device can be configured to support any type of communicationsprotocol desired.

With continued reference to FIG. 10, the PCIe controller(s) 1010 maycommunicate with one or more PCIe devices 1020 such as the PCIeendpoints 104(1)-104(M) of FIG. 1 and the PCIe endpoints 904(1)-904(4)of FIG. 9 through one or more PCIe interfaces 1022 or the PCIe buses 106and 908.

Those of skill in the art will further appreciate that the variousillustrative logical blocks, modules, circuits, and algorithms describedin connection with the aspects disclosed herein may be implemented aselectronic hardware, instructions stored in memory or in anothercomputer-readable medium and executed by a processor or other processingdevice, or combinations of both. The devices described herein may beemployed in any circuit, hardware component, integrated circuit (IC), orIC chip, as examples. Memory disclosed herein may be any type and sizeof memory and may be configured to store any type of informationdesired. To clearly illustrate this interchangeability, variousillustrative components, blocks, modules, circuits, and steps have beendescribed above generally in terms of their functionality. How suchfunctionality is implemented depends upon the particular application,design choices, and/or design constraints imposed on the overall system.Skilled artisans may implement the described functionality in varyingways for each particular application, but such implementation decisionsshould not be interpreted as causing a departure from the scope of thepresent disclosure.

The various illustrative logical blocks, modules, and circuits describedin connection with the aspects disclosed herein may be implemented orperformed with a processor, a Digital Signal Processor (DSP), anApplication Specific Integrated Circuit (ASIC), a Field ProgrammableGate Array (FPGA) or other programmable logic device, discrete gate ortransistor logic, discrete hardware components, or any combinationthereof designed to perform the functions described herein. A processormay be a microprocessor, but in the alternative, the processor may beany conventional processor, controller, microcontroller, or statemachine. A processor may also be implemented as a combination ofcomputing devices (e.g., a combination of a DSP and a microprocessor, aplurality of microprocessors, one or more microprocessors in conjunctionwith a DSP core, or any other such configuration).

The aspects disclosed herein may be embodied in hardware and ininstructions that are stored in hardware, and may reside, for example,in Random Access Memory (RAM), flash memory, Read Only Memory (ROM),Electrically Programmable ROM (EPROM), Electrically ErasableProgrammable ROM (EEPROM), registers, a hard disk, a removable disk, aCD-ROM, or any other form of computer readable medium known in the art.An exemplary storage medium is coupled to the processor such that theprocessor can read information from, and write information to, thestorage medium. In the alternative, the storage medium may be integralto the processor. The processor and the storage medium may reside in anASIC. The ASIC may reside in a remote station. In the alternative, theprocessor and the storage medium may reside as discrete components in aremote station, base station, or server.

It is also noted that the operational steps described in any of theexemplary aspects herein are described to provide examples anddiscussion. The operations described may be performed in numerousdifferent sequences other than the illustrated sequences. Furthermore,operations described in a single operational step may actually beperformed in a number of different steps. Additionally, one or moreoperational steps discussed in the exemplary aspects may be combined. Itis to be understood that the operational steps illustrated in themessage flow and flowchart diagrams may be subject to numerous differentmodifications as will be readily apparent to one of skill in the art.Those of skill in the art will also understand that information andsignals may be represented using any of a variety of differenttechnologies and techniques. For example, data, instructions, commands,information, signals, bits, symbols, and chips that may be referencedthroughout the above description may be represented by voltages,currents, electromagnetic waves, magnetic fields or particles, opticalfields or particles, or any combination thereof.

The previous description of the disclosure is provided to enable anyperson skilled in the art to make or use the disclosure. Variousmodifications to the disclosure will be readily apparent to thoseskilled in the art, and the generic principles defined herein may beapplied to other variations without departing from the spirit or scopeof the disclosure. Thus, the disclosure is not intended to be limited tothe examples and designs described herein, but is to be accorded thewidest scope consistent with the principles and novel features disclosedherein.

What is claimed is:
 1. A method of passing information in a PeripheralComponent Interconnect (PCI) express (PCIe) system, comprising:receiving at a host a signal from a PCIe endpoint comprising: a header;and a body comprising: extended message signaled interrupt (MSI) messagedata comprising a system level identifier for the PCIe endpoint set bythe host and indicating interrupt authorization in at least one of afirst sixteen bits; and MSI message data in at least one of a secondsixteen bits; wherein the first sixteen bits are between the header andthe second sixteen bits; extracting, at a root complex of the host, thebody from the signal to form an MSI vector with the extended MSI messagedata still in a body of the MSI vector; and passing over an internal busthe MSI vector to an interrupt controller in the host with the extendedMSI message data still in the body of the MSI vector.
 2. The method ofclaim 1, wherein receiving at the host the signal comprising the headercomprises receiving at the host the signal comprising a requesteridentifier in the header.
 3. The method of claim 1, wherein receiving atthe host the body comprising the extended MSI message data comprisesreceiving the body comprising interrupt priority information.
 4. Themethod of claim 1, further comprising extracting, at the interruptcontroller, the system level identifier from the extended MSI messagedata prior to acting on the MSI message data.
 5. The method of claim 1,wherein receiving at the host the body comprising the extended MSImessage data comprises receiving the body comprising additional messagedata.
 6. The method of claim 1, further comprising configuring the PCIeendpoint with the system level identifier prior to receiving at the hostthe signal.
 7. The method of claim 1, further comprising inquiring, fromthe host to the PCIe endpoint, whether the PCIe endpoint is capable ofsending the extended MSI message data.
 8. The method of claim 1, furthercomprising configuring the interrupt controller in the host to use theextended MSI message data in the body of the MSI vector.
 9. The methodof claim 1, wherein the internal bus comprises a system bus.
 10. A hostin a Peripheral Component Interconnect (PCI) express (PCIe) system,comprising: an internal bus; a PCIe bus interface configured to becoupled to a PCIe bus, wherein the PCIe bus interface is furtherconfigured to receive a signal from the PCIe bus comprising: a header;and a body comprising: extended message signaled interrupt (MSI) messagedata in at least one of a first sixteen bits comprising a system levelidentifier for a PCIe endpoint set by the host; and MSI message data inat least one of a second sixteen bits; an interrupt controller coupledto the internal bus; a memory management unit coupled to the internalbus; and a root complex coupled to the PCIe bus interface and the memorymanagement unit, wherein the root complex is configured to extract thebody from the signal to form an MSI vector with the extended MSI messagedata still in a body of the MSI vector and pass the MSI vector to theinterrupt controller with the extended MSI message data still in thebody of the MSI vector through the memory management unit and theinternal bus; wherein the interrupt controller is configured todetermine whether to act on the MSI message data based on the systemlevel identifier.
 11. The host of claim 10, wherein the internal buscomprises a system bus.
 12. A Peripheral Component Interconnect (PCI)express (PCIe) system, comprising: a PCIe bus; a PCIe slave comprising:a slave PCIe bus interface coupled to the PCIe bus; a slave controlsystem configured to: detect an interrupt need condition; assemble asignal comprising: a header; and a body comprising:  extended messagesignaled interrupt (MSI) message data in at least one of a first sixteenbits comprising a system level identifier for the PCIe slave set by ahost and indicating interrupt authorization; and  MSI message data in atleast one of a second sixteen bits; and send the signal to the host overthe PCIe bus; and the host comprising: an internal bus; a host PCIe businterface coupled to the PCIe bus, wherein the host PCIe bus interfaceis further configured to receive the signal; an interrupt controllercoupled to the internal bus; and a root complex coupled to the host PCIebus interface, wherein the root complex is configured to extract thebody from the signal to form an MSI vector with the extended MSI messagedata still in a body of the MSI vector and pass the MSI vector to theinterrupt controller with the extended MSI message data still in thebody of the MSI vector through the internal bus.
 13. The PCIe system ofclaim 12, wherein the internal bus comprises a system bus.
 14. A methodof identifying a signal source in a Peripheral Component Interconnect(PCI) express (PCIe) system, comprising: receiving at a host a signalfrom a Peripheral Component Interconnect (PCI) express (PCIe) endpointcomprising: a header having a requester identifier; and a bodycomprising: a source identifier for the PCIe endpoint set by the host inat least one of a first sixteen bits; and message signaled interrupt(MSI) message data in at least one of a second sixteen bits; at a rootcomplex of the host, removing the requester identifier; extracting thebody to form an MSI vector with the source identifier still in a body ofthe MSI vector; and passing over an internal bus the MSI vector to aninterrupt controller in the host with the source identifier still in thebody of the MSI vector.
 15. The method of claim 14, further comprisingusing the source identifier at the interrupt controller to verify thePCIe endpoint as authorized to request an interrupt.
 16. The method ofclaim 14, further comprising initiating a capability query at the hostto the PCIe endpoint.
 17. The method of claim 16, further comprisingreceiving a response to the capability query from the PCIe endpointindicating the PCIe endpoint is capable of using the source identifierin the body of the signal.
 18. The method of claim 17, furthercomprising instructing the PCIe endpoint to enable use of the sourceidentifier in the body of the signal.
 19. The method of claim 14,further comprising configuring the interrupt controller to read thesource identifier in the body of the MSI vector.
 20. A method ofidentifying a signal source, comprising: receiving at a host a signalfrom a Peripheral Component Interconnect (PCI) express (PCIe) endpointcomprising: a header having a requester identifier; and a bodycomprising: a system level identifier for the PCIe endpoint set by thehost in at least one of a first sixteen bits; and message signaledinterrupt (MSI) message data in at least one of a second sixteen bits;at a root complex of the host, removing the requester identifier;extracting the body to form an MSI vector with the system levelidentifier still in a body of the MSI vector; and passing over aninternal bus the MSI vector to an interrupt controller in the host withthe system level identifier still in the body of the MSI vector.
 21. Themethod of claim 20, wherein the internal bus comprises a system bus. 22.A method of passing information in a Peripheral Component Interconnect(PCI) express (PCIe) system, comprising: receiving at a host, from aPCIe endpoint, a signal comprising: a header; and a body, wherein thebody comprises: a first sixteen reserved bits having extended messagesignaled interrupt (MSI) message data in at least one of the firstsixteen reserved bits and comprising a system level identifier for thePCIe endpoint set by the host; and a second sixteen bits having MSImessage data in at least one of the second sixteen bits; extracting, ata root complex of the host, the body from the signal to form an MSIvector with the extended MSI message data still in a body of the MSIvector; passing over an internal bus the MSI vector to an interruptcontroller in the host with the extended MSI message data still in thebody of the MSI vector; and determining, at the interrupt controller,whether to act on the MSI message data based on the system levelidentifier.